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oct . , 20 11 v0 . 15 p f 7 5223 f7 522 3 bios guard release date: oct 20 1 1 version: v0. 1 5 p
oct . , 20 11 v0 . 15 p f 7 5223 f 75223 datasheet revision history version date page revision history v0.10p 20 1 1 / 8 - preliminary version v0.11p 2011/ 8 26 update application circuit v0.12p 2011/ 8 -- typo correction v0.13 p 2011/ 09 -- update package information / register descirption. v0.14p 2011/10 -- update package information / register descirption. v 0.15p 2011/11 -- update register description v0.16p 2012/01 -- add new function description please note that all data an d specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support applianc es, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify fintek for any damages resulting from such improper use or sales. table of content
oct . , 20 11 v0 . 15 p f 7 5223 1. general description ................................ ................................ ................................ .............. 4 2. feature list ................................ ................................ ................................ ........................... 4 3. key specification ................................ ................................ ................................ ................... 5 4. bloc k diagram ................................ ................................ ................................ ....................... 5 5. pin configuration ................................ ................................ ................................ .................. 6 6. pin description ................................ ................................ ................................ ...................... 7 power pin ................................ ................................ ................................ ........................... 7 smbus interface ................................ ................................ ................................ ............... 7 host spi interface ................................ ................................ ................................ .............. 7 slave spi interface ................................ ................................ ................................ ............. 7 system signal interface ................................ ................................ ................................ ..... 8 flash status ................................ ................................ ................................ ........................ 8 7. function description ................................ ................................ ................................ ............. 8 7.1 power on tra pping ................................ ................................ ................................ ..... 8 7.2 spi ................................ ................................ ................................ .............................. 8 7.3 system signal ................................ ................................ ................................ ............. 9 7.4 flash strap and status ................................ ................................ ............................... 10 7.5 wdt ................................ ................................ ................................ .......................... 11 7.6 auto refreshing ................................ ................................ ................................ ........ 12 8. register description ................................ ................................ ................................ ............ 15 9. electrical characteristics ................................ ................................ ................................ ..... 21 9.1 absolute maximum ratings ................................ ................................ ...................... 21 9.2 dc characteristics ................................ ................................ ................................ .... 21 9.3 ac characteristics ................................ ................................ ................................ .... 22 10.ordering information ................................ ................................ ................................ .......... 24 11.top marking specification ................................ ................................ ................................ .. 24 12.package dimensions ................................ ................................ ................................ ......... 25 13.application cir cuit ................................ ................................ ................................ .............. 26
j an . , 20 1 2 v0 . 1 6 p 4 f 7 5223 1. general description the f 75223 is a bios guard which can copy the bios code from one spi flash to another . the f 75223 provide s an interface to connect 2 spi flash es and supports manual /auto mode option. mode option c an be decide d by hardware strapping (by pwrok pin) or register setting . two spi flash es can be assumed to flash a and flash b . f or manual mode, the f 75223 control s flash a or b to read or program by the spi host which means only one flash could be accessed by the spi host. f or auto mode, the f 75223 sequen tially control s flash a and b to read or program by the spi host. f75223 provide s a watch dog timer and pwrok detect function . when system power on, the wdt function will count down to zero and the pwrok st atus would be detected in the meantime . t imeout or the pwrok failure will trigger the reset signal to the system and sequen tially change to backup flash for booting . also , the f75223 would alternate the flash when pwrok failure occurs . the f 75223 is progra mmed by smbus interface , and only support byte read/write protocol. the chip is powered by vsb and packaged in 20 qfn green spec. 2. feature list general functions ? bi - directional bios recover y ? m anual copy by button ( low pu lse, de - bounce 4 seconds ) ? s trap status when pwrok rising and load to state machine immediately ? 4 mode s of led status blinking (a, b, burn in from b to a or a to b ) ? wdt timer ( 1sec ~ 16sec, default 10sec ) ? pwrok counter ? power - down mode ? p rogrammable spi comma nd, register include c hip e rase command (0xc7) read command (0x03) program command (0x02) write enable command (0x06) write disable command (0x04) read status command (0x05) enable write status command (0x50) write status command (0x01) long wait time r egister package ? 20 - pin qf n green package
j an . , 20 1 2 v0 . 1 6 p 5 f 7 5223 3. key specification supply voltage 3.0v to 3.6v maximum operation supply current (vsb) 5 m a max . idl e current (vsb) 3 .5 m a max . power down mode current (vsb) 10u a max vbat current (operation / id el / power down) < 1ua 4. block diagram host core controler wdt i2c interface access point flash b flash a power down control internal 34mhz clock led control F75223N
j an . , 20 1 2 v0 . 1 6 p 6 f 7 5223 5. pin configuration pwrok gnd vsb hcs# hclk rstout# smdat smclk cs2# cs1# led button vbat funsel0 funsel1 clk mosi miso hmiso hmosi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 f75223
j an . , 20 1 2 v0 . 1 6 p 7 f 7 5223 6. pin description i input, 5v tolerance in st,5v ttl level input pin and schmitt trigger, 5v tolerance. o output, 5v tolerance o 1 6 output pin with 1 6 ma sink capability. od 12 , 5v open drain, 12ma sink capability, 5v tolerance i i /od 12st,5v ttl level bi - directional pin and schmitt trigger,open - drain output with 12 ma source - sink capability, 5v tolerance. p power pin power pin pin no. pin name type description 2 gnd p ground . 3 vsb p 3v power. 18 v bat p 3v power smbus interface pin no. pin name type pwr description 1 3 smclk i / o d 12st,5v vsb smb us clock . 1 4 smdat i / o d 12st,5v vsb smb us data . host spi interface pin no. pin name type pw r description 4 hcs# i vsb spi chip select from master. 5 hclk i vsb master spi clock. 6 hmosi i vsb master data out and slave data input. 7 hmiso o vsb master data in and slave data out. slave spi interface pin no. pin name type pwr description 8 m iso i vsb master data in put and slave data out put . (bypass mode) in st,5v master data in put and slave data out put . ( refresh mode) 9 mosi o vsb master data out put and slave data input. (bypass mode) o 1 6 master data out put and slave data input with 1 6 m a sink capability . (re fresh mode) 10 clk o vsb slave spi clock. (bypass mode) o 1 6 slave spi clock with 1 6 ma sink capability . (re fresh mode) 11 cs1# o vsb spi chip select 1. (bypass mode) o 1 6 spi chip select 1 with 1 6 ma sink capability . (re fresh mod e) 12 cs2# o vsb spi chip select 2. (bypass mode) o 1 6 spi chip select 2 with 1 6 ma sink capability . (re fresh mode)
j an . , 20 1 2 v0 . 1 6 p 8 f 7 5223 system signal interface pin no. pin name type pwr description 1 pwrok in st,5v vsb power ok signal input from sio . 1 5 rstout# od 12 ,5v v sb reset output. flash strap and s tatus pin no. pin name type pwr description 1 6 led od 12 ,5v vsb led output signal, indicate current block. 1 7 button in st,5v vsb i nput signal for manual back up flash, de - bounce 4s. strap smbus address when vsb power on . 20 ,1 9 funsel [1:0] in st,5v vsb funsel0: s trap flash block when pwrok rising. (1: a flash / 0: b flash) funsel1: s trap auto or manual when pwrok rising. (1: auto mode / 0: manual mode) 7. function description 7.1 st rapping function the f 75223 provides 3 pins of hardware power on strapping to select functions . t here is a form to describe how to set the functions you want. t hese pin will strap signal when vsb power on or pwrok rising. table 7. 1 .1 . power on strapping configuration p in no. symbol value description t rapping by 17 button - p ull high 100k to select smbus address 0x58 vsb - p ull high 1k to select smbus address 0x96 vsb 19 funsel 0 1 p ull high 1k to select a block pwrok 0 pull down 1k to select b block pwrok 20 funsel 1 1 p ull high 1k to select aut o mode pwrok 0 pull down 1k to select manual mode pwrok 7.2 spi the f 75223 c ould work in two modes, bypass mode and auto refresh spi flash mode. t he default function is bypass mode. in the situation that the main block flash (block a) crashed , the f 75223 will assert a rstout# signal to the system and switch to the block b flash. w hen bios detects the system is using s econdary (block b) flash . the bios can refresh the flash from block b to block a , by send ing a command to f 75223 . when refreshing. the stat us of
j an . , 20 1 2 v0 . 1 6 p 9 f 7 5223 bios recovery burn - in can be tracked from f75223 s register. after refreshing, then the bios can assert a full reset command from io base 0xcf9 . figure 7.2.1 describe what is spi signal source for spi flash. figure 7. 2 .1 sp i signal path diagram 7.3 system signal 7.3.1 rstout# w hen wdt timeout occurs , the f75223 will send a rstout# signal to the system. t he rstout# can be set to assert the reset signal once or twice . t he rstout# issued low pulse least 200 ms. t he high time space betw een first pulse and second pulse is 1 second. figure 7. 5 .1 show as rstout s status after wdt timeout occurs . 7.3.2 pwrok after the f75223 receive the pwrok signal from sio . a counter inside the f75223 count s the rising edges of pwrok . t he f75223 will switch the flash from one to another, if the counter exceeds the limit threshold that set by the user . w hen the wdt _en at index 0x02 was disable by host, the pwrok_value at index 0x0a would be clear to zero. pwrok is also be used to control power - on strapping, the f unsel pin s will strap signals when pwrok rising. figure 7. 3 . 2.1 show as pwrok counter exceeds the high limit illustrator . figure 7.3.2.1 pwrok counter exceeds the high limit illustrator (when the pwrok_cnt at index 0x0ah has be set to 4) refresh flash control bypass mode spi flash a spi flash b host f75223 pwrok wdt count down count down count down count down wdt_en funsel[1:0] auto a wdt disable auto b count down
j an . , 20 1 2 v0 . 1 6 p 10 f 7 5223 7.4 flash strap and status 7.4.1 led there are four types of led status which can indicate which flash block is beening used or the f75223 is refreshing bios. . table 7. 4 .1 . 1 led status table led status d escription tri - state block a is in use s ink low blco k b is in use 10 hz pulse r efreshing from b to a 1 hz pulse r efreshing from a to b 7.4.2 function select pin funsel is the strap pin which controls the beheavers of f75223 when a bios error occurs. table 7. 4 .1 . 1 function select status table fun sel[1:0] d esc ription 11 auto mode, using block a flash as primary bios storage device. when an error occurs, it will a utomaticaly switch the flash from block a to b lock b . 10 auto mode, using block b flash as primary bios storage device. when an error occurs, it wil l a utomaticaly switch the flash from block b to block a . 01 manual select block a flash. it won a uto mode: t he f75223 will iss ue rstout# to system and switch to the alternate flash device. m anual mode: in manual mode. the system will only use the selected flash block to boot - up and the bios error protection mechanism are been disabled. 7.4.3 button f75223 provides a button pin let use r can refresh the flash from b to a or f rom a to b. the button de - bounce time is 4 s econds . when the button is press ed low for more than 4 seconds, the f75223 will set a start bit and auto refresh the flash block. t here are 2 correspond features of f75223 bios refersh function. the button event can sink the rstout# signal low till the burn - in process been finished. also, the f75223 can assert rstout# to the system when the burn - in flash finish. figure 7. 4 . 3.1 and figure 7.4.3. 2 show how the rstout# actual behaves when the burn - in spi flash starts .
j an . , 20 1 2 v0 . 1 6 p 11 f 7 5223 figure 7.4.3.1 button illustrator with rstout# sink low figure 7.4.3. 2 button illustrator with rstout# low pulse 7.5 wdt wdt, the watch dog timer counting i s range from 1 ~ 16 seconds (default 10 sec ). it can be reset by pwrok low level signal and re - start counting again after pwrok rising. i n auto mode , and pwrok happened , the wdt will default enable. i n manual mode, the wdt will default disable. the f75223 wil l issue rstout# to system if the wdt timeout. figure 7. 5 .1 and figure 7. 5 . 2 show as rstout s status after wdt happened timeout . figure 7.5.1 wdt timeout illustrator with tw o low pulse of rstout > 4sec button rstout# sink low refresh process > 4sec button rstout# refresh process 300msec count down to zero(auto a) wdt timer count down(auto b) 200msec 200msec 1sec rstout# (twice) wdt_en count down(auto a) pwrok wdt di sable
j an . , 20 1 2 v0 . 1 6 p 12 f 7 5223 fig ure 7.5. 2 wdt timeout illustrator with single low pulse of rstout (default) 7.6 auto refreshing t he auto - refreshing would include erase function, read function and program function. t he f75223 would support a complete auto - refreshing. u sers only set the start bit for auto - refreshing (bit 7 at index 03h) or the button has been press low for more than 4 seconds after the flash size, spi frequency, the destination of program would be set. t he figure 7. 6 .1 show s as auto - refresh process flow. count down to zero(auto a) wdt timer count down(auto b) 300msec rstout# (once) wdt_en pwrok wdt di sable
j an . , 20 1 2 v0 . 1 6 p 13 f 7 5223 figure 7. 6 .1 describe rstout s status and flash block status after wdt happened timeout . chip erase flash check flash busy read flash program flash check flash busy refresh finish start bit flag is low issue rstout# set flash size set spi frequency set the destination of program set start bit or button low yes no yes no wait time wait time chag_en and rtsout_en at index 0x04 w ere enable chag_en at index 0x04 w as disable, rstout_en at index 0x04 w as enable yes yes no no flash block change and issue rstout# yes no
j an . , 20 1 2 v0 . 1 6 p 14 f 7 5223 7.7 auto power down mode f75223 provides an auto power saving feature ( default d isable ). user may e n able this function, then the f75223 will go into power down mode au tomatically . i f none of the six wakeup events (refresh enable, wdt enable, smbus busy, rstout low pulse, button pin low and pwrok rising edge) be asserted , the power down control module w ill count down to zero for power down internal clock (default 2 sec.) . the f75223 will return to work, if one of th os e six wakeup events has been triggered , and stops the power down control module. the register at index 0x0bh controls the timing of count down. t he figure 7. 7 .1 describe s how the system power down. figure 7. 7 .1 power down control illustrator pow er dow n control refresh enable wdt enable sm bus busy pwrok rising edge rstout low pulse button pin low wakeup event pow er dow n internal clock
j an . , 20 1 2 v0 . 1 6 p 15 f 7 5223 8. register description 8.1 flash control 8 . 1.1 flash status register C index 00h bit name r/w default description 7 am_st r - t he bit always show s the strap status of selected mo de configuration. (auto or manual mode , funsel0 pin ). 6 bk_st r - t he bit always show s the strap status of selected primary block. ( a block flash or b block flash , funsel1 pin ). 5 get _ am r 0 h this bit shows the smbus modified mode configuration . this bit shows the corresponding setting status of am_sel bit at index01h. 4 g et_bk r 0 h this bit shows the smbus modified block configuration. this bit shows the corresponding setting status of bk_sel bit at index01h. 3 wdt_to fag r 0 h t he flag would be set to 1, when the wdt count down to zero . w rite 1 to clear th is bit. 2 p wrok_to fag r 0 h t he flag would be set to 1, when the counter exceeds the high limit. w rite 1 to clear th is bit. 1 a cs_fag r 0 h w hen host accessed register at index 01h by smbus interface, the flag would be set to 1. w rite 1 to clear th is bit. 0 reserve - - reserve 8 . 1. 2 flash control register C index 0 1 h bit name r/w default description 7 - 2 reserve - - reserve 1 am_ sel r/w - f75223 control flash status by am_sel ( auto or manual mode). 1: auto mode 0: manual mode 0 bk_ sel r / w - f75223 control flash block by bk_sel (a block flash or b block flash). 1: a block flash 0: b block flash if acs_fag flag at index 0 0 h has be set to 1 and reboot of system , the am_sel register at index 01h wil l ignore the strap s etting (funsel0 pins). acs_fag flag at index 0 0 h must be clear d to 0 and reboot of system, the am_sel register at index 01h will then follow the strap s etting (funsel0 pin). in the conditional that one of flags (wdt_to, pwrok_to, acs_ fag at index 00h) has be set to 1, the bk_sel register at index 01h will ignore the strap setting (funsel1 pin). all the flags (wdt_to, pwrok_to, acs_fag at index 00h) must be cleard to 0 and reboot of system, the bk_sel register at index 01h will then fol low the strap setting (funsel1 pins).
j an . , 20 1 2 v0 . 1 6 p 16 f 7 5223 8. 2 wdt control 8 . 2.1 wdt control register C index 0 2 h bit name r/w default description 7 wdt_en r/w 0 h w hen pwrok rising happened, the bit would be set to 1. 6 rstout_sel r/w 0 h 0: rstout# would issue one low puls e. 1: rstout# would issue tw o low pulse. 5 - 4 reserve - - reserve 3 - 0 wdt_sec r/w 9h t he wdt would count down to zero with wdt_sec timing. 0 0 00 : 1sec 0001 : 2sec 0010 : 3sec 0011 : 4sec 1001 : 10sec (default) 1110 : 15sec 1111 : 16sec 8. 3 auto refresh cont rol 8 . 3.1 auto refresh control 1 register C index 0 3 h bit name r/w default description 7 refh_en r/w 0h w hen users set the bit to 1 or button pin has been press ed low for more than 4 seconds, the auto - refresh function would auto refresh the crashed flash. if the bit was set to 1, f75223 would refresh spi flash. 6 - 4 size_sel r/w 1 h u sers would select the spi flash s size by the register. 00 0 : 1mbyte 00 1 : 2mbyte (default) 010 : 4mbyte 011 : 8mbyte 100 : 16mbyte others : reserve 3 dn_pram r/w 0 h u sers would set the destination of program by the register. 0: b block flash copy to a block flash. 1: a block flash copy to b block flash. 2 - 0 freq_sel r/w 3 h u sers would select spi frequency in auto - refresh mode by the register. 000 : 34mhz (duty cycle is not 50%) 001 : 17mhz ( d uty cycle is 50% ) 010 : 8mhz ( d uty cycle is 50% ) 011 : 4 mhz ( d uty cycle is 50% , default ) 100 : 1 mhz ( d uty cycle is 50% ) others : reserve 8 . 3.2 auto refresh control 2 register C index 0 4 h bit name r/w default description 7 - 6 reserve - 0 h reserve
j an . , 20 1 2 v0 . 1 6 p 17 f 7 5223 5 c hag_en r/w 0h w hen the bit and rtsout_en must be set to 1 and auto - refresh has finish, the flash block would change to another flash block . a lso, the rstout# would issue the low pulse to system. 4 rtsout_en r/w 0 h w hen the bit has be set to 1 and auto - ref resh has finish, the rstout# would issue the low pulse to system. 3 c r _pwrok r/w 1 h i f the bit was set to 1 and pwrok has be 1, the bypass mode would be enable by f75223. a lso, the bit was set to 0, the bypass mode wouldn t care pwrok signal. 2 sst_en r/ w 0 h set this bit to 1, if the flash been recovered is a sst flash . 1 s ink l_en r/w 0 h w hen the bit was set to 1 and auto - refresh was processing , rstout# would sink low until auto - refresh finish. 0 flash_b u s y r 0 h w hen t he bit was set to 1, f75223 would e rasing or program ing flash now . 8 . 3. 3 wait time high byte register C index 0 5 h bit name r/w default description 7 - 0 wait_timeh r/w 10h w hen flash has be busy, the auto - refresh state match would wait. 8 . 3. 4 wait time low byte register C index 0 6 h bit n ame r/w default description 7 - 0 wait_timel r/w 9ch w hen flash has be busy, the auto - refresh state match would wait. 0x109c indicate state match would wait 4253 refreshed clock cycles. 8 . 3.5 refresh status high byte register C index 0 7 h bit name r/w defa ult description 7 - 0 perc_h r/w 00h percentage of auto - refresh precess status. ( high byte r egister ) 8 . 3.6 refresh status medium byte register C index 0 8 h bit name r/w default description 7 - 0 perc_m r/w 00h percentage of auto - refresh precess status.( mediu m byte r egister ) 8 . 3.7 refresh status low byte register C index 0 9 h bit name r/w default description 7 - 0 perc_l r/w 00h percentage of auto - refresh precess status.( low byte r egister ) t he percentage of auto - refresh process status show as index 0x07h, 0 x08h and 0x09h. table 7.3.1 describle s how the of refresh progress be shown in regesters . table 7. 3 . 1 p ercentage of auto - refresh precess status f lash size perc ({perc_h,perc_m , perc_l ) percentage perc(sst flash) percentage 1m 0f , ff , 00 h 100% 0f , ff , ffh 100% 00 , 00 , 00 h 0% 00 , 00 , 00h 0% 2m 1f , ff , 00 h 100% 1f , ff , ffh 100%
j an . , 20 1 2 v0 . 1 6 p 18 f 7 5223 00 , 00 , 00 h 0% 00 , 00 , 00h 0% 4m 3f , ff , 00 h 100% 3f , ff , ffh 100% 00 , 00 , 00 h 0% 00 , 00 , 00h 0% 8m 7f , ff , 00 h 100% 7f , ff , ffh 100% 00 , 00 , 00 h 0% 00 , 00 , 00h 0% 16m ff , ff , 00 h 100% ff , ff , ffh 100% 00 , 00 , 00 h 0% 00 , 00 , 00h 0% 8. 4 pwrok timeout control 8 . 4 .1 pwrok timeout control register C index 0 a h bit name r/w default description 7 - 5 pwrok_value r 0h this t he register show as happened pwrok times when system would not process into os yet. when the wdt _en at index 0x02 was disable by host, the pwrok_value would be clear to zero . 6 - 3 reserve - r eserve 2 - 0 pwrok _ cnt r/w 4 h w hen the register was set to 4 and pwrok counter exceed 4 times (5th) , the f75223 would change another flash. 8 . 4.2 power down co ntrol register C index 0 b h bit name r/w default description 7 pd_en r/w 0h when the bit was set to 1, system would begin to count down to zero. 6 - 0 pd_sec r/w 32h i f wakeup event didn t happen, system would count pd_sec timing. 0000000b : reserve 011000 0b : reserve 0110001b : reserve 0110010b : ~ 2.04sec (default) 0110011b : ~ 2.08sec 0110100b : ~ 2.12sec 1111110b : ~ 5.08sec 1111111b : ~ 5.12sec 8. 5 instruction control 8 . 5.1 write enable instruction register C index 10 h bit name r/w default description 7 - 0 wre n r/w 06h write enable instruction . 8 . 5.2 chip erase instruction register C index 11 h bit name r/w default description
j an . , 20 1 2 v0 . 1 6 p 19 f 7 5223 7 - 0 ce r/w c7h chip erase instruction . 8 . 5. 3 read status instruction register C index 12 h bit name r/w default description 7 - 0 read _stus r/w 05h read status register instruction . 8 . 5.4 read instruction register C index 13 h bit name r/w default description 7 - 0 read r/w 03h read instruction . 8 . 5.5 write disable instruction register C index 14 h bit name r/w default description 7 - 0 wrdis r/w 04h write disable instruction . 8 . 5.6 program instruction register C index 15 h bit name r/w default description 7 - 0 prgm r/w 02h program instruction . 8 . 5.7 enable write status register instruction register C index 16 h bit name r/w default des cription 7 - 0 enwrstus r/w 50h enable write status register instruction. 8 . 5.8 write status register instruction register C index 17 h bit name r/w default description 7 - 0 wrstus r/w 01h write status register instruction. 8 . 5.9 reserve register C index 18 h bit name r/w default description 7 - 0 reserve - 00h reserve 8 . 5.9 reserve register C index 19 h bit name r/w default description 7 - 0 reserve - 00h reserve 8 . 5.9 reserve register C index 1a h bit name r/w default description 7 - 0 reserve - 0 1 h reser ve 8. 6 chip number
j an . , 20 1 2 v0 . 1 6 p 20 f 7 5223 8 . 6.1 chip id1 register C index 5a h bit name r/w default description 7 - 0 chip_id1 r 11h chip id1 8 . 6.2 chip id2 register C index 5b h bit name r/w default description 7 - 0 chip_id2 r 07h chip id2 8 . 6.4 vender id1 register C index 5d h bit name r/w default description 7 - 0 vender_id1 r 19h vender id1 8 . 6.4 vender id2 register C index 5e h bit name r/w default description 7 - 0 vender_id2 r 34h vender id2
j an . , 20 1 2 v0 . 1 6 p 21 f 7 5223 9. electrical characteristics 9.1 absolute maximum ratings parameter rating unit power supply voltage - 0. 5 to 5.5 v input voltage - 0. 5 to vcc +0. 5 v operating temperature 0 to + 70 ? c storage temperature - 55 to 150 ? c note: exposure to conditions beyond those listed under absolute maximum ratings may adverse ly affect the life and reliability of the device 9.2 dc characteristics (ta = 0 ? c to 70 ? c, vcc = 3.3v ? 10% , vss = 0v ) parameter rating operating voltage 3.0 to 3.6 vcc operating voltage 2.4 to 3.6 vbat parameter sym. min typ max. unit conditions i/o d 12st5v - open - drain output pin with 12ma source - sink capability(3.3v) and schmitt trigger , 5v tolerance input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol 12 ma 0.4v input high leakage ilih - 1 1 ? a input low leakage ilil - 1 1 ? a o d 12st5v - open - drain output pin with 12ma so urce - sink capability, 5v tolerance output low current iol 12 ma 0.4v i/o 12st5v - ttl level bi - directional pin with 4 ma source - sink capability(3.3v) and schmitt trigger , 5v tolerance input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol 12 ma 0.4v output high current ioh 12 ma 2.4v input high leakage ilih - 1 1 ? a input low leakage ilil - 1 1 ? a o 16 - open - drain output pin with 1 6 ma source - s ink capability, 5v tolerance
j an . , 20 1 2 v0 . 1 6 p 22 f 7 5223 output low current iol 16 ma 0.4v i C ttl level input pin and schmitt trigger, 5 v tolerance input low threshold voltage 0.8 v input hign threshold voltage 2.0 v hysteresis 0.5 v input high leakage +1 ? a input low leakage - 1 ? a 9.3 ac characteristics 9.3.1 smbus interface serial bus timing parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.7 us stop condition setup - up time t su;sto 4.7 us data to scl setup time t su;dat 120 ns data to scl hold time t hd;dat 5 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns valid data scl sda in sda out t hd;sda t scl t hd;dat t su;st o t su;dat serial bus timing diagram t r t r
j an . , 20 1 2 v0 . 1 6 p 23 f 7 5223 9.3.2 spi interface spi timing parameter symbol min. max. unit /cs not active hold time relative to clk t chsl 5 n s data in setup time t dvch 2 n s /cs active setup time relative to clk t slch 5 n s data in hold time t chdx 5 ns clock rise time peak to peak t clch 0.1 v/ ns /cs active hold time relative to clk t chsh 10 n s /cs de select time t shsl 100 ns /cs not active setup time relative to clk t shch 0 ns clock fall time peak to peak t chcl 0.1 v/ ns 9.3.3 internal clock description typ. unit internal clock 36 20% mhz /cs clk hmosi tchsl m sb in tslch tdvch tchdx lsb in tshsl tshch tchsh tclch tchcl hmiso high impedance spi timing diagram
j an . , 20 1 2 v0 . 1 6 p 24 f 7 5223 10. ordering information 11. top marking specification the version identification is shown as the bold red three characters. please refer to below table for detail: part nu mber package type production flow f 75223 n 20 - qf n green package commercial, 0 ? c to +70 ? c 223n 1 st line: device name ? 223n , where n means the package code 2 nd line: week code (xx) + fintek internal code (xx) + ic version (x) where a means version a, b means version b, 3 rd line: waf er fab code (xxxxx) : pin 1 identifier xxx x x xxx x x
j an . , 20 1 2 v0 . 1 6 p 25 f 7 5223 12. package dimensions 20 qfn feature integration technolog y inc. headqua r ters taipei office 3f - 7 , no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o. c. tel : 886 - 3 - 5600168 tel : 866 - 2 - 8227 - 8027 fax : 886 - 3 - 5600166 fax : 866 - 2 - 8227 - 8037 www: http://www.fintek.com.tw please note that all datasheet and s pecifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r pin 21 (ep)
j an . , 20 1 2 v0 . 1 6 p 26 f 7 5223 13. application circuit pwrok vsb3v r3 1k spi_mo pwrok pch_sy stem_reset pch_smbus_data pch_smbus_clk vsb3v r1 1k funsel1 funsel0 spi_so r7 x_0 r8 x_0 r11 0 pwrok pch_spi_clk pch_spi_cs# ledout pch_spi_clk vsb3v pch_spi_mo spi_mo spi_clk pch_spi_so vsb3v pch_spi_cs# spi_so spi_mo spi_clk button_in net name lo hi spi_so funsel0 funsel1 auto mode a block manual mode b block r14 33 vsb3v r10 x_1k r15 33 pch_spi_mo r16 33 r17 33 r18 33 vbat vsb3v r19 33 r2 1k ce# 1 so 2 wp# 3 vss 4 si 5 sck 6 hold# 7 vdd 8 u1 w25q32 spi_cs1# spi_hold# ce# 1 so 2 wp# 3 vss 4 si 5 sck 6 hold# 7 vdd 8 u3 w25q32 spi_cs2# spi_hold# r4 1k pch_smbus_clk vsb3v pch_spi_so pch_smbus_data vsb3v spi_cs2# led status description tri-state current block is a sink low current block is b 10 hz pulse refreshing from b to a 1 hz pulse refreshing from a to b vsb3v spi_cs1# vsb3v 1 2 sw1 r9 100k pch_sy stem_reset vbat r6 1k r5 1k title size document number rev date: sheet of F75223N module board 0.1 feature intergration technology inc b 1 1 tuesday , october 18, 2011 pull high 100k : 0x58 funsel1 funsel0 spi_clk button_in vsb3v pull high 1k : 0x96 smbus address ledout r12 330 d2 led pch_sy stem_reset pwrok 1 gnd 2 vsb 3 hcs# 4 hclk 5 hmosi 6 hmiso 7 miso 8 mosi 9 clk 10 cs1# 11 cs2# 12 smclk 13 smdat 14 rstout# 15 led 16 button 17 vbat 18 funsel0 19 funsel1 20 F75223N u2 F75223N qfn 4x4mm trapping switch 1 2 + 4.7u c1 1 2 c2 1u 2 1 j1 li-bat socket d1 diode

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